The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of ion implantation and a method of fabricating a semiconductor device which increases the production yield of the semiconductor device.
A semiconductor memory device such as a dynamic random access memory (DRAM) stores data in and reads data from a plurality of memory cells. The semiconductor memory device includes a plurality of bit lines and a plurality of word lines. The semiconductor memory device also includes a circuit for selecting a bit line and a word line. The semiconductor memory device further includes peripheral circuits, such as a sense amplifier, for sensing data read from a memory cell and for amplifying the data to a predetermined level.
The memory cell of the DRAM includes an access transistor and a capacitor. The data stored in the capacitor is transmitted to the bit line through the access transistor when the word line connected to the gate terminal of the access transistor is selected. The data is transmitted to a sense amplifier through the bit line. The sense amplifier senses and amplifies the data. The data is then transmitted to an input/output line. Data input through the input/output line is also amplified by the sense amplifier and written in the memory cell.
FIG. 1 is a circuit diagram showing an example of a conventional semiconductor memory device.
A semiconductor memory device 100 includes a pair of bit lines BL and /BL, a bit line equalizer 110, a sense amplifier 120, a column selection gate 130, a latch signal generator 140, and a sense amplifier activating circuit 150. The bit lines BL and /BL are connected to a memory cell MC to transmit data. The bit line equalizer 110 receives a precharge voltage VBL and equalizes the pair of bit lines BL and /BL to a same voltage level. The sense amplifier 120 senses and amplifies the data transmitted through the pair of bit lines BL and /BL. The column selection gate 130 is connected to a column selection line CSL to connect the pair of bit lines BL and /BL and input/output lines IO and /IO. The latch enable signal generator 140 receives the precharge voltage VBL and generates P-sense amplification and N-sense amplification latch enable signals LA and /LA to control the sense amplifier 120. The sense amplifier activating circuit 150 is connected to the latch enable signal generator 140.
The memory cell MC includes an access transistor connected to an intersection between the word line and the bit line, and a capacitor connected between the access transistor and a substrate voltage VP.
The sense amplifier 120 includes a P-sense amplifier and an N-sense amplifier. The P-sense amplifier includes PMOS transistors 121 and 122 connected between the pair of bit lines BL and /BL in series. The PMOS transistors 121 and 122 have gate terminals respectively cross-connected to the pair of bit lines BL and /BL and source terminals for receiving the P-sense amplification latch enable signal LA. The N-sense amplifier includes NMOS transistors 123 and 124 connected between the pair of bit lines BL and /BL in series. The NMOS transistors 123 and 124 have gate terminals respectively cross-connected to the pair of bit lines BL and /BL and source terminals for receiving the N-sense amplification latch enable signal /LA.
The sense amplifier 120 includes four MOS transistors. Left and right transistors connected between the bit line BL and the bit line bar /BL are simultaneously driven. In other words, the threshold voltages of the left and right transistors are substantially identical. However, during operation of the transistors, the left and right transistors may not be simultaneously activated due to a variation in the threshold voltage between the left and right transistors. The sensing margin of the sense amplifier depends on offset characteristics, which depends on the difference between threshold voltages of the left and right transistors.
The left and right transistors are different from each other in a bump failure rate of a semiconductor memory device.
FIG. 2 is a graph showing a bump failure rate vs. the position of a transistor included in a sense amplifier of a semiconductor memory device. A horizontal axis indicates the transistor and a vertical axis indicates the number of bump failures. Reference numerals “U0” and “U1” respectively indicate the left and right transistors located at an upper side, and reference numerals “L0” and “L1” respectively indicate the left and right transistors located at a lower side.
The bump failure rates of the right transistors are larger than those of the left transistors. In addition, the threshold voltages of the right transistors are larger than those of the left transistors. Thus, the characteristics of the device significantly deteriorate.
The difference between the threshold voltages of the transistors included in the sense amplifier deteriorates the offset characteristics of the sense amplifier, thereby adversely affecting the production yield of the device.